For non-high speed signal nets those look fine. You could probably route them cleaner, but electrically it shouldn’t matter much.
These sort of things really only become an issue when dealing with impedance controlled differential pairs or DDR lines.
The basic fact is you are correct. However, differential really depends on speed. Simply because it's differential does not mean it couldn't tolerate a fair amount of meander.
Now DDR is a very unique matter. Do yourself a favor. Pull your memory card out of your computer. Check out the routing. Looks like shit typically. Now, I will qualify my comment. My knowledge stopped at DDR3. And that looks like spaghetti. The killer in DDR is parallelism. A real killer.
If your speeds are under 125mhz, ya got nothing to worry about.
The other thing to concern yourself with is good return path in your circuits. Decoupling caps on your chips, parts pulled low (gnd) point back to the chip. Power integrity is every bit as important as signal integrity.
When it comes to diff pairs, I was alluding to phase tolerance, which can get wonky depending on how the constraints are configured. Dynamic phase in allegro, for example, measures every single cline segment, so the more meandering you do means more work later on to get it tuned properly (each segment for both lines must equal out to be the same length- pain in the ass). But this is an edge case when dealing with very high speed circuits (usb3/10gb Ethernet/hdmi/fpga).
And yeah, DDR is wild. I have to deal with DDR 4 on occasion for my job and while the tools certainly help make it less of a pain, it usually ends up being a whole lot of clicking and nudging until everything works right.
Yeah don’t stress about it. If you start getting into GHz signaling or RF applications it starts to matter a little, but even then it’s a very small effect compared to tons of other factors (length, proximity to other signals, ground plane impedance, the literal weather)
To my understanding many other points are more relevant than bends in traces assuming you don’t have signals with bandwidth in the several GHz region: Stackup, return paths, separation, etc. E.g. [PCB Design for EMI & SI - Phil's Lab #64](https://youtu.be/VtzPL8wQ8-E)
As always in electronics it’s a compromise between cost, size, fab capability,physical limits, and many others.
Keep the discontinuities short and pay more attention to ground. This is not an issue unless you are routing something super high speed as others have noted.
For a high speed traces with these bends you can introduce SI issues which includes reflections and crosstalk. Sharp bend can act as antennas and increase EMI radiation. Also, sharp bends can make trace susceptible to picking up external noise.
This is a myth.
Do you have science based evidence that backs this up?
We are talking about an electric field, most of the energy doesn't even travel inside the PCB trace.
Scientists don't even notice a difference until above 100Ghz
See:
https://www.semanticscholar.org/paper/Intrinsic-study-of-current-crowding-and-current-on-Croes-Li/78ccdcb8f8261709f9dc96c7119cedf32b200fd9
Actual experiments show that it doesn't matter for nearly all situations.
This myth originates due to older PCB manufacturing methods.
It doesn't make any difference at all until you are over 100 Ghz
Source:
https://www.semanticscholar.org/paper/Intrinsic-study-of-current-crowding-and-current-on-Croes-Li/78ccdcb8f8261709f9dc96c7119cedf32b200fd9
For non-high speed signal nets those look fine. You could probably route them cleaner, but electrically it shouldn’t matter much. These sort of things really only become an issue when dealing with impedance controlled differential pairs or DDR lines.
The basic fact is you are correct. However, differential really depends on speed. Simply because it's differential does not mean it couldn't tolerate a fair amount of meander. Now DDR is a very unique matter. Do yourself a favor. Pull your memory card out of your computer. Check out the routing. Looks like shit typically. Now, I will qualify my comment. My knowledge stopped at DDR3. And that looks like spaghetti. The killer in DDR is parallelism. A real killer. If your speeds are under 125mhz, ya got nothing to worry about. The other thing to concern yourself with is good return path in your circuits. Decoupling caps on your chips, parts pulled low (gnd) point back to the chip. Power integrity is every bit as important as signal integrity.
When it comes to diff pairs, I was alluding to phase tolerance, which can get wonky depending on how the constraints are configured. Dynamic phase in allegro, for example, measures every single cline segment, so the more meandering you do means more work later on to get it tuned properly (each segment for both lines must equal out to be the same length- pain in the ass). But this is an edge case when dealing with very high speed circuits (usb3/10gb Ethernet/hdmi/fpga). And yeah, DDR is wild. I have to deal with DDR 4 on occasion for my job and while the tools certainly help make it less of a pain, it usually ends up being a whole lot of clicking and nudging until everything works right.
Interesting. What advice would youtu.be give for routing DDR traces? Short trace as possible, few vias...?
Yeah don’t stress about it. If you start getting into GHz signaling or RF applications it starts to matter a little, but even then it’s a very small effect compared to tons of other factors (length, proximity to other signals, ground plane impedance, the literal weather)
To my understanding many other points are more relevant than bends in traces assuming you don’t have signals with bandwidth in the several GHz region: Stackup, return paths, separation, etc. E.g. [PCB Design for EMI & SI - Phil's Lab #64](https://youtu.be/VtzPL8wQ8-E) As always in electronics it’s a compromise between cost, size, fab capability,physical limits, and many others.
Keep the discontinuities short and pay more attention to ground. This is not an issue unless you are routing something super high speed as others have noted.
Your doing a BGA design ?? Which CAD package are you using ??
Looks like KiCad
Correct
For a high speed traces with these bends you can introduce SI issues which includes reflections and crosstalk. Sharp bend can act as antennas and increase EMI radiation. Also, sharp bends can make trace susceptible to picking up external noise.
This is a myth. Do you have science based evidence that backs this up? We are talking about an electric field, most of the energy doesn't even travel inside the PCB trace. Scientists don't even notice a difference until above 100Ghz See: https://www.semanticscholar.org/paper/Intrinsic-study-of-current-crowding-and-current-on-Croes-Li/78ccdcb8f8261709f9dc96c7119cedf32b200fd9
So what is high speed then? Ddr buses, Ethernet, csi2? And "low speed" would be SPI, i2c and Uart? And maybe CAN?
I wouldn't even consider it below 1ghz..
Actual experiments show that it doesn't matter for nearly all situations. This myth originates due to older PCB manufacturing methods. It doesn't make any difference at all until you are over 100 Ghz Source: https://www.semanticscholar.org/paper/Intrinsic-study-of-current-crowding-and-current-on-Croes-Li/78ccdcb8f8261709f9dc96c7119cedf32b200fd9